1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device and a method for manufacturing the same, in which structures of a gate electrode and a gate line prevent a data line and a drain electrode from being open at crossing areas (step difference) overlapped with the gate line and the gate electrode, respectively.
2. Discussion of the Related Art
Recently, with the increasing development of an information-based society, demands for various display devices have increased. Accordingly, much effort has been expended to research and develop various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD), and some species of the flat display devices are already applied to displays of various equipment.
Among the various flat display devices, the liquid crystal display (LCD) device has been most widely used due to advantageous characteristics of thinness, lightness in weight, and low power consumption, whereby the LCD device substitutes for Cathode Ray Tube (CRT). In addition to the mobile type LCD devices such as a display for a notebook computer, the LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.
Despite various technical developments in the LCD technology with applications in different fields, research in enhancing the picture quality of the LCD device has been in some respects lacking as compared to other features and advantages of the LCD device. In order to use the LCD device in various fields as a general display, the key to developing the LCD device lies on whether the LCD device can implement a high quality picture, such as high resolution and high luminance with a large-sized screen while still maintaining lightness in weight, thinness, and low power consumption.
The LCD device includes an LCD panel for displaying a picture image, and a driving part for applying a driving signal to the LCD panel. The LCD panel includes first and second glass substrates bonded to each other at a predetermined interval, and a liquid crystal layer injected between the first and second glass substrates.
The first glass substrate (TFT array substrate) includes a plurality of gate and data lines, a plurality of pixel electrodes, and a plurality of thin film transistors. The plurality of gate lines are formed on the first glass substrate at fixed intervals in one direction, and the plurality of data lines are formed at fixed intervals in perpendicular to the plurality of gate lines. Then, the plurality of pixel electrodes of a matrix arrangement are respectively formed in pixel regions defined by the plurality of gate and data lines crossing each other. The plurality of thin film transistors are switched according to signals of the gate lines for transmitting signals of the data lines to the respective pixel electrodes.
The second glass substrate (color filter substrate) includes a black matrix layer excluding light from regions except the pixel regions of the first substrate, R/G/B color filter layer displaying various colors, and a common electrode displaying the picture image. Next, a predetermined space is maintained between the first and second glass substrates by spacers, and the first and second substrates are bonded to each other by a sealant. Then, the liquid crystal layer is injected into the inner space of the sealant. When manufacturing an LCD device having the aforementioned structure, a plurality of LCD panels are formed on one large substrate in due consideration of sizes of the LCD panel and the substrate, simultaneously.
More specifically, an LCD device according to the related art will be described as follows.
FIG. 1 is an enlarged plan view illustrating a unit pixel region of an LCD device according to the related art. As shown in FIG. 1, a gate line 1 is formed at a fixed interval in one direction on a lower substrate (not shown), and a gate electrode 1a projects from the gate line 1 in one direction. At this time, a storage lower electrode of a storage capacitor is formed in one body as the preceding gate line 1. That is, the preceding gate line 1 serves as the storage lower electrode.
Then, a gate insulating layer (not shown) is formed on the lower substrate including the gate line 1 and the gate electrode 1a, and a data line 2 is formed on the gate insulating layer for being in perpendicular to the gate line 1, thereby defining a pixel region. Subsequently, a source electrode 2a is projecting from the data line 2, and a drain electrode 2b is formed at a fixed interval from the source electrode 2a. At this time, the source electrode 2a is formed in a ‘⊂’-shaped hollow, and the drain electrode 2b is formed inside the ‘⊂’-shaped hollow apart from the source electrode 2a at the fixed interval, whereby a ‘⊂’-shaped channel region is defined between the source electrode 2a and the drain electrode 2b. 
Next, an active layer 3 having a predetermined shape is patterned on the gate insulating layer. In this state, the active layer 3 is formed below the data line 2, the source electrode 2a and the drain electrode 2b to have a size enough for covering the data line 2, the source electrode 2a and the drain electrode 2b. That is, the size of the active layer 3 is larger than a size including the data line 2, the source electrode 2a and the drain electrode 2b. The active layer 3 is formed by sequentially depositing an amorphous silicon layer and n+ amorphous silicon layer. Then, a storage upper electrode 2c is formed at one portion of the preceding gate line 1 serving as the storage lower electrode.
After that, a passivation layer (not shown) is formed on an entire surface of the lower substrate, the passivation layer having a first contact hole 4a at one portion of the drain electrode 2b, and a second contact hole 4b at one portion of the storage upper electrode 2c. Then, a pixel electrode 5 is formed in the pixel region that is in contact with the drain electrode 2b through the first contact hole 4a, and in contact with the storage upper electrode 2c through the second contact hole 4b. Subsequently, a conductive layer is deposited on the gate insulating layer, and then a wet-etch process is performed thereto, thereby forming the data line 2, the source electrode 2a and the drain electrode 2b. 
However, the LCD device and the method for manufacturing the same according to the related art have the following disadvantages.
When the gate electrode 1a is shifted, an overlapped crossing area between the gate line 1 and the data line 2 is changed, whereby signal distortion may be generated by a change in the capacitance Cgd. Also, as shown in ‘A’ region of FIG. 1, when patterning the data line, the source electrode and the drain electrode by the wet-etch process, the crossing area (step difference) between the gate line 1 and the data line 2 has a narrow width (arrow ⇄). As a result, the data line 2 of the crossing area may be corroded by the etchant, thereby generating disconnection of the lines.
Furthermore, as shown in ‘B’ region of FIG. 1, since an overlap area (step difference) between the gate electrode 1a and the drain electrode 2b has a narrow width (arrow ⇄), the drain electrode 2b of the overlap area may be corroded by the etchant, thereby generating disconnection.